SOVEREIGNBENCH :: OPEN DETERMINISM STANDARD

Hardware Determinism Leaderboard

Public hardware benchmark ranking silicon architectures and kernel supervisory substrates by worst-case execution time (WCET), p99 APIC interrupt jitter (ns), and synchronous Ring-0 IPC clock cycles. Lower is strictly superior.

SUBMIT YOUR SILICON TELEMETRYAuto-registers on global leaderboard
curl -sSL https://arom-one.vercel.app/bench.sh | sh

Active Benchmark Index

Sorted by p99 Latency (Lowest Jitter First)
14 Verified Submissions
RankSilicon TargetCoresSupervisor Kernelp99 JitterIPC CyclesStatus
1Intel Xeon 6 6980P (128 Cores Granite Rapids)128CARKM 12-Core SMP (Ring-0)36.4 ns104VERIFIED
2AMD EPYC 9655 (96C/192T Zen 5 Turin)96CARKM 12-Core SMP (Ring-0)38.2 ns108VERIFIED
3Apple Silicon M2 Ultra (24 Cores AIC2)24CARKM Microkernel (Direct Vector)39.1 ns98VERIFIED
4IIT Madras Shakti H-Class (64-bit RISC-V)16CARKM Bare-Metal PLIC/AIA42.5 ns101VERIFIED
5Intel(R) Core(TM) i3-7020U CPU @ 2.30GHz4CLinux Native42.8 ns114VERIFIED
6Intel Core i9-14900KS (Raptor Lake Refresh)24CARKM SMP Dedicated P-Core43.8 ns112VERIFIED
7IIT Madras Shakti C-Class (Indigenous RISC-V)8CARKM Bare-Metal PLIC Native46.2 ns105VERIFIED
8AMD EPYC 9654 (96C/192T Zen 4)96CARKM Ring-0 Affinity Locked49.3 ns116VERIFIED
9C-DAC Vega ET1061 (Octa-Core RISC-V)8CARKM Sovereign Substrate50.4 ns108VERIFIED
10Ampere AmpereOne A192-32X (192 Cores)192CARKM GICv4.1 Direct Virtual51.0 ns112VERIFIED
11Intel Xeon Gold 6338 (32C/64T Ice Lake)32CLinux 6.8 RT-PREEMPT64.8 ns126VERIFIED
12AMD EPYC 7763 (64C/128T Milan)64CLinux 6.8 RT-PREEMPT68.2 ns128VERIFIED
13Intel Xeon Platinum 8480+ (56C/112T)56CGeneric Monolithic Linux (Ubuntu 24.04)142.5 ns230VERIFIED
14Intel Core i9-14900KS (Standard Workstation)24CWindows Server 2025 (NT Ring-0)285.0 ns410VERIFIED

p99 APIC Interrupt Jitter

Measures worst-case temporal deviation when an APIC timer hardware interrupt preempts a running userspace thread. Sub-45ns indicates hard real-time mission compliance.

Ring-0 IPC Clock Cycles

Calculates CPU core clock cycles required to execute a synchronous microkernel capability context switch (int \$0x80) and return to the caller.

DAP 2026 Audit Requirement

Critical defense avionics and naval fire-control systems mandate bounded non-stochastic jitter profiles to meet DO-178C DAL-A flightworthiness specifications.